#Digital works direct generator

Therefore, the correction of the ADC characteristics and especially linearization are important for obtaining high characteristics of the receiver (in particular, sensitivity).

Moreover, spurious-free dynamic range (SFDR) is important, because the less harmonics at the ADC output, the less the probability of blocking the desired low signals by these harmonics and less unwanted received components. e., the more SNDR, the more sensitive the receiver is, because noise floor is lower. In there is a clear correspondence between the sensitivity and signal-to-noise and distortion (SNDR) of the ADC, i.

FPGA stands for Field Programmable Gate Array. The goal of this study is to provide the linearization of an analog-to-digital converter (ADC) for an FPGA-based direct digital receiver. Petersburg State Polytechnical University Journal. Linearization of the Analog-to-Digital Converter for an FPGA-based Direct Digital Receiver. Keywords: pipelined ADC, digital error calibration and correction, MATLAB, SFDR, FPGA.Д¬itation: Krneta M., Piatak I.M. LINEARIZATION OF THE ANALOG-TO-DIGITAL CONVERTER FOR AN FPGA-BASED DIRECT DIGITAL RECEIVER The influence of changes in the DC gain and capacitor mismatch of MDAC inside the stage was also taken into account for both SNDR and SFDR, as well as for the static characteristic, INL, which was also observed.ДOI: 10.18721/JCSTCS.10304 UDC 621.3.049.774.2 The influence of the DC gain and that of the capacitors of the MDAC was taken into account and observed. The values of the dynamic characteristics of the ADC (SNDR and SFDR) were obtained before and after calibration, and compared.

#Digital works direct generator

The DDS generator was implemented inside the FPGA. Its calibration and LUT-based correction were performed using both MATLAB/Simulink and FPGA. The experimental part consists of the implementation of the FPGA-based parametrized 14-bit model pipelined ADC using MATLAB/Simulink. One of the techniques for implementing that is the LUT-based calibration and correction technique inside the FPGA, which was used for obtaining better characteristics of SNDR, SFDR and INL of the FPGA-based parametrized 14-bit model of pipelined ADC.

The goal of this work is to provide linearization of the analog-to-digital converter for an FPGA-based Direct Digital Receiver.